Conventionally, in a matrix-type liquid crystal display device, an organic electroluminescence (EL) display device and a plasma display device, a timing controller LSI chip, which successively generates and outputs one horizontal line of a grayscale data signal and scanning signal from one frame of image signals, and a source driver LSI chip, which serves as a driver unit that receive the grayscale data signal and drive respective ones of data lines of a display panel, are mounted on a printed circuit board. Transmission of signals between the timing controller LSI chip and the source driver LSI chip, as well as transmission of signals between the source driver LSI chips that are cascade-connected, is achieved by transmission lines consisting of printed conductor. An LVDS (Low Voltage Differential Signaling) interface, for example, is a high-speed interface used as the transmission circuit.
As shown in FIG. 11, the conventional transmitter circuit of an LVDS interface includes a constant-current source 6 having one end connected to a high-potential power supply VDD; a constant-current source 7 having one end connected to a low-potential power supply VSS; an N-channel MOS transistor N1 and an N-channel MOS transistor N2 serving as switching means connected serially between the other end of the constant-current source 6 and the other end of the constant-current source 7; an N-channel MOS transistor N3 and an N-channel MOS transistor N4 serving as switching means connected serially between the other end of the constant-current source 6 and the other end of the constant-current source 7; a non-inverting output terminal 2 connected to the node of the N-channel MOS transistor N1 and N-channel MOS transistor N2; and an inverting output terminal 3 connected to the node of the N-channel MOS transistor N3 and N-channel MOS transistor N4. A terminating resistor of a receiver circuit is connected between the non-inverting output terminal 2 and inverting output terminal 3 via a pair of transmission lines, and a voltage comparator of the receiver circuit recognizes signal logic by discriminating the voltage across the terminating resistor. A CMOS-level non-inverted input data signal supplied to an input terminal 1 is applied to the gate terminal of the N-channel MOS transistor N1 and to the gate terminal of the N-channel MOS transistor N4. An inverting input data signal, which is a result of the non-inverted input data signal being inverted by the CMOS-type inverter circuit 5, is applied to the gate terminal of the N-channel MOS transistor N2 and to the gate terminal of the N-channel MOS transistor N3. When the non-inverted input data signal is at the VDD level serving as logic H, the N-channel MOS transistors N1 and N4 turn on, the N-channel MOS transistors N2 and N3 turn off, loop signal current flows from the constant-current source 6 to the constant-current source 7 via the N-channel MOS transistor N1, non-inverting output terminal 2, transmission line, terminating resistor, transmission line, inverting output terminal 3 and N-channel MOS transistor N4, and the receiver circuit recognizes the logic H level. When the non-inverted input data signal is at the VSS level serving as logic L, the N-channel MOS transistors N1 and N4 turn off, the N-channel MOS transistors N2 and N3 turn on, loop signal current in the opposite direction flows from the constant-current source 6 to the constant-current source 7 via the N-channel MOS transistor N3, non-inverting output terminal 3, transmission line, terminating resistor, transmission line, non-inverting output terminal 2 and N-channel MOS transistor N2, and the receiver circuit recognizes the logic L level.
Patent Document 1
    Japanese Patent Kokai Publication No. JP-P2000-31810A (FIG. 13)